R-28 (2021 version).

Fully balanced and fully discrete headphone amplifier and pre-amplifier all-in-one.

Built-in fully balanced amp/preamp, output power up to 9500mW, enough to drive most earphones.

Fully discrete parts are truly balanced current transmission design..

4 sets of fully discrete individual DSD hardware decoders..

8 sets of fully discrete R-2R DA modules form a two-channel balanced push-pull decoder..

Two Accusilicon clocks with frequencies up to 90/98MHz provide the complete machine synchronization clock without the need for PLL upscaling.

32bit / 384K asynchronous transmission Amanero USB interface, using FPGA to synchronize the clock.

USB / HDMI supports DXD and DSD.

The digital circuit of the whole machine is composed of 1 piece of FPGA and 5 pieces of CPLD programmable device, which separates different functional circuits to isolate interference.

The parallel data processing mode with the fastest transmission speed is applied, and the firmware upgrade is supported to improve the sound quality effect.

All digital mode settings can be done on the panel (no need to turn on the machine).

The main board uses the Accusilicon clocks:

Features of R-28 (2021version):

1. USB not only transmits the IIS signal to the FPGA processor, but also receives the synchronous clock signal sent by the FPGA processor. The USB interface itself is no longer equipped with a data clock. The use of a synchronous clock makes the signal transmission more accurate and greatly improves the sound quality close to the previous generation R -28 plus DI-20 (but not DI-20HE) sound quality effects. (New upgrade)

3. The FPGA data processing mode is parallel processing mode.

The IIS signal is a serial data mode. Each data requires one clock cycle. One frame of left and right channel data requires 64 clock cycles, which is affected by the stability of 64 clock cycles.

Parallel mode only needs one clock to transmit and process the 32-bit data of the left and right channels, which greatly improves the processing speed and is less affected by the stability of the clock.

IIS input data (USB and HDMI-IIS) is immediately reorganized into two sets of 32-bit parallel data as soon as it is input. After the SPDIF signal is demodulated, it is also sent to the next level of processing through two sets of 24-bit parallel data. DSD data is also reorganized into two groups of 64-bit parallel data processing as soon as it is input.

After contrast listening, the parallel processing mode can make the sound clearer and neutral, with better dynamics and more analog flavor.

4. The clock management design of the new architecture makes the clock work more stable, with higher transparency and richer details.

5. DSD uses the built-in asynchronous clock to re-calibrate,

6. SPDIF supports DOP playback.

7. Two transformers supply power separately.

8. The product has two levels of gain. The low gain of 12DB is suitable for driving earphones with sensitivity above 95DB, and the high gain of 22DB, with strong output power, is enough to drive earphones of around 85DB.

The advantages and disadvantages of R-2R DAC:

Advantages:

1, R-2R will not convert the clock signal to the output signal.

2, R-2R is not sensitive to jitter but Delta-Sigma is quite sensitive.

3. The accuracy of the output signal level of R-2R is higher than that of Delta-Sigma.

Disadvantages:

1. R2R's harmonic distortion can be quite low, but it can't achieve low harmonic distortion like ES9038 PRO (Delta-Sigma).

2, The accuracy of glitch and step resistance is not easy to solve.

Accuracy of step resistance:

24 bit is already a standard, but can the precision of the resistor that can be manufactured reach 24 bit?

Even if it is 16 bit, the accuracy requirement is 1/66536, and even 0.1% (1/1000) of resistance accuracy is completely inadequate. Even if it is 0.01% (1/10000), it still fails to meet the 16 bit requirement, let alone 24 bit.

Therefore, the accuracy of the resistance is not the direction to solve the problem. If there is a 0.00001% resistance in the world, it can meet the requirement of 24 bit, but the discreteness of the internal resistance of the step resistance switch will completely wipe out the advantage of this super high accuracy.

Very important FPGA/CPLD:

FPGA/CPLD is a programmable logic array device.

Nowadays, FPGA has been used in many Hi-End level DAC products, like the popular ROCKNA WAVEDREAM DAC.

Since 2008, we have used FPGA design in DAC products.

This machine consists of 1 piece of FPGA and 5 pieces of CPLD chip to form the digital circuit of the whole machine.

The hardware layout inside FPGA can be designed and arranged through software, and the hardware can be upgraded through software update.

When the firmware is upgraded, the hardware will be upgraded at the same time. This design has a high degree of flexibility. It can improve the sound quality through software upgrades, add more updated functions, and make the product never lag behind the times.

Responsible FPGA/CPLD:

1. The FPGA has a built-in high-performance SPDIF demodulator instead of the low-performance SPDIF demodulator chips on the market such as DIR9001, WM8805 and AK411X.

2. Recombined clock and FIFO technology, output data can be accurately synchronized to the clock, rejecting jitter.

3. Built-in 2X, 4X and 8X digital filters, and different algorithm NOS modes allow users to choose the tone that best suits their personal taste.

4. Simulate the sound of TDA1541+SAA7220 through a unique design.

Volume characteristic: